In order to reduce overall power consumption in a circuit, it is well known to scale the supply voltage. However, reducing the supply voltage of the circuit leads to lowering the speed of metal-oxide-semiconductor (MOS) devices in the circuit. In order to maintain circuit performance, MOS device threshold voltages (Vt) must scale with the supply voltage, which will cause subthreshold leakage currents to increase exponentially. Multiple-threshold complementary metal-oxide-semiconductor (MTCMOS) circuit architectures have been demonstrated as an effective technique for reducing leakage currents during a standby state by employing high threshold voltage “sleep” devices to gate one or more voltage supplies (e.g., VDD, ground, etc.) of a logic block employing low threshold voltage devices.
FIG. 1 shows a typical MTCMOS circuit implementation, wherein a logic cell 102 including low threshold voltage devices is connected between a voltage supply rail, VDD, and a virtual ground, VGND, and a high threshold voltage switching cell comprising an n-channel MOS (NMOS) device, MSLP, is connected between the virtual ground VGND and an actual ground rail, GND. Device MSLP is gated by a control signal, SLEEP, which turns off MSLP during a standby mode to reduce leakage currents generated by the logic cell 102 by isolating the logic cell from the actual ground rail.
Conventional MTCMOS circuit implementations typically utilize switching cells which are in-line with standard logic cells to connect the virtual ground to the actual ground rail. Using this layout approach, however, requires that both the virtual ground and the actual ground rail be carried throughout the standard logic cells, resulting in a silicon area penalty for essentially the entire standard logic cell library.
Accordingly, there exists a need for an improved power switching cell arrangement which does not suffer from one or more of the problems exhibited by conventional power switching cell arrangements.